EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 120

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
6–20
Cyclone III Device Handbook, Volume 1
inclk0
inclk1
clkswitch
areset
pfdena
c[4..0]
clkbad[1..0]
locked
activeclock
Table 6–6. PLL Input Signals
Table 6–7. PLL Output Signals
Port
Port
PLL output counters driving global or external
clocks.
Signals indicating which reference clock is no longer
toggling.
clkbad0 indicates
1 = good; 0 = bad
Lock output from lock detect circuit. Active high.
Signal to indicate which clock (0=inclk0 or 1=inclk1)
is driving the PLL. If this signal is low, inclk0 drives
the PLL. If this signal is high, inclk1 drives the PLL.
Clock input to the PLL.
Clock input to the PLL.
Switchover signal used to initiate external clock
switchover control. Active high.
Signal used to reset the PLL, which resynchronizes
all the counter outputs. Active high.
Enables the outputs from the phase frequency
detector. Active high.
Table 6–6
“PLL Reconfiguration” on page 6–37
time PLL reconfiguration ports and dynamic phase shifting.
clkbad1
inclk0
Description
Description
and
indicates
Table 6–7
status.
inclk1
describe all the basic PLL ports. Please refer to
status,
for additional information on real-
Dedicated input
clock pin or
another PLL
Dedicated input
clock pin or
another PLL
Logic array
Logic array
Logic array
PLL counter
PLL switch-
over circuit
PLL lock detect Logic array
PLL clock
multiplexer
Altera Corporation- Preliminary
Source
Source
Clock switchover
circuit
Clock switchover
circuit
PLL switchover
circuit
General PLL
control signal
PFD
Internal or external
clock (only c0)
Logic array
Logic array
Destination
Destination
March 2007