EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 369
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Altera Corporation-Preliminary
March 2007
You can set a lower clock frequency by specifying a division factor in the
Quartus II software (refer to
divisor is a power of two (2), where n is between 0 and 8. The divisor
ranges from 1 through 256. See the following equation:
CRC calculation time depends on the device and the error detection clock
frequency.
with minimum and maximum clock frequencies for Cyclone III devices.
Notes to
(1)
(2)
Error detection frequency =
Device
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
Table 13–5. CRC Calculation Time
The minimum time corresponds to the maximum error detection clock frequency
and may vary with different processes, voltages, and temperatures.
The maximum time corresponds to the minimum error detection clock frequency
and may vary with different processes, voltages, and temperatures.
Table
Table 13–5
13–5:
Minimum Time (ms)
shows the estimated time for each CRC calculation
80MHz
----------------- -
2
n
“Software Support” on page
15
23
31
45
5
5
7
9
Cyclone III Device Handbook, Volume 1
(1)
Maximum Time (s)
Error Detection Timing
11.77
15.81
22.67
2.29
2.29
3.17
4.51
7.48
13–8). The
(2)
13–7
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