EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 133
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F256I7N
Manufacturer:
IR
Quantity:
14 520
Company:
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA31
Quantity:
214
Part Number:
EP3C16F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 133 of 582
- Download datasheet (7Mb)
Figure 6–19. VCO Switchover Operating Frequency
Phase-Shift
Implementation
Altera Corporation-Preliminary
March 2007
■
Phase shift is used to implement a robust solution for clock delays in
Cyclone III devices. Phase shift is implemented by using a combination of
the VCO phase output and the counter starting time. The VCO phase
output and counter starting time is the most accurate method of inserting
delays, since it is purely based on counter settings, which are
independent of process, voltage, and temperature.
You can phase shift the output clocks from the Cyclone III PLLs in either:
■
■
Fine resolution phase shifts are implemented by allowing any of the
output counters (C[4..0]) or the m counter to use any of the eight
phases of the VCO as the reference clock. This allows you to adjust the
delay time with a fine resolution. The minimum delay time that you can
insert using this method is defined by:
Φ
where f
fine
Disable the system during switchover if it is not tolerant to frequency
variations during the PLL resynchronization period. You can use the
clkbad[0] and clkbad[1] status signals to turn off the PFD
(pfdena = 0) so the VCO maintains its last frequency. You can also
use the switch over state machine to switch over to the secondary
clock. Upon enabling the PFD, output clock enable signals (clkena)
can disable clock outputs during the switchover and
resynchronization period. Once the lock indication is stable, the
system can re-enable the output clock(s)
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
= 1/8 T
REF
is input reference clock frequency.
VCO
=1/8f
vco
= N/8Mf
ref
Cyclone III Device Handbook, Volume 1
Phase-Shift Implementation
6–33
Related parts for EP3C16F256I7N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: