EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 301

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
f
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 80 µs). After nSTATUS is released and pulled high by a pull-up resistor,
the MAX II device can try to reconfigure the target device without
needing to pulse nCONFIG low. If this option is turned off, the MAX II
device must generate a low-to-high transition (with a low pulse of at least
500 ns) on CONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but the
CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
1
When the device is in user-mode, initiating a reconfiguration is done by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 500 ns. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. When
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
For more information about configuration issues, refer to the Debugging
Configuration Problems chapter of the Configuration Handbook and the
FPGA Configuration Troubleshooter on the Altera web site at
www.altera.com.
Figure 10–21
device. This circuit is similar to the FPP configuration circuit for a single
device, except the Cyclone III devices are cascaded for multi-device
configuration.
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 80 µs).
shows how to configure multiple devices using a MAX II
Cyclone III Device Handbook, Volume 1
Fast Passive Parallel Configuration
10–65