EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 375

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Introduction
Altera Corporation-Preliminary
March 2007
CIII5014-1.0
As PCBs become more complex, the need for thorough testing becomes
increasingly important. Advances in surface-mount packaging and PCB
manufacturing have resulted in smaller boards, making traditional test
methods (such as external test probes and "bed-of-nails" test fixtures)
harder to implement. As a result, cost savings from PCB space reductions
increase the cost for traditional testing methods.
In the 1980s, the JTAG developed a specification for boundary-scan
testing that was later standardized as the IEEE Std. 1149.1 specification.
This boundary-scan test (BST) architecture offers the ability to efficiently
test components on PCBs with tight lead spacing.
BST architecture tests pin connections without using physical test probes
and captures functional data while a device is operating normally.
Boundary-scan cells in a device can force signals onto pins or capture data
from pin or logic array signals. Forced test data is serially shifted into the
boundary-scan cells. Captured data is serially shifted out and externally
compared to expected results.
Figure 14–1. IEEE Std. 1149.1 Boundary-Scan Testing
This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in
Cyclone
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Serial
Data In
IEEE Std. 1149.1 BST architecture
IEEE Std. 1149.1 boundary-scan register
IEEE Std. 1149.1 BST operation control
I/O voltage support in JTAG chain
Using IEEE Std. 1149.1 BST circuitry
®
III devices, including:
JTAG Device 1
Boundary-Scan Cell
Logic
Core
Boundary-Scan Testing for
IC
14. IEEE 1149.1 (JTAG)
Figure 14–1
Connection
Pin Signal
Tested
Cyclone III Devices
illustrates the concept of BST.
JTAG Device 2
Logic
Core
Preliminary
Serial
Data Out
14–1