EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 381

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

IEEE Std. 1149.1
BST Operation
Control
Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
(4)
User I/O pins
Dedicated clock
input
Dedicated input
(3)
Dedicated
bidirectional
(open drain)
Dedicated
output
SAMPLE/PRELOAD
EXTEST
Table 14–3. Cyclone III Device Boundary Scan Cell Descriptions
Table 14–4. Cyclone III JTAG Instructions
Pin Type
TDI, TDO, TMS, TCK, all V
No Connect (N.C.).
This includes pins nCONFIG, MSEL0, MSEL1, MSEL2, MSEL3, and nCE.
This includes pins CONF_DONE and nSTATUS.
JTAG Instruction
Table
(1)
(4)
14–3:
OUTJ
0
0
0
OUTJ
Register
Capture
Output
CC
Instruction Code
Cyclone III devices support the IEEE Std. 1149.1 (JTAG) instructions
shown in
00 0000 0101
00 0000 1111
and GND pin types do not have BSCs.
Captures
OEJ
1
1
OEJ
0
Register
Capture
OE
Table
PIN_IN PIN_OUT
PIN_IN
PIN_IN
PIN_IN
0
Register
Capture
Input
14–4.
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins. Also used by
the SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing
test results at the input pins.
Allows a snapshot of signals at the device pins to be captured
N.C.
N.C.
N.C.
N.C.
Register
Update
Output
(2)
(2)
(2)
(2)
Note (1)
PIN_OE
N.C.
N.C.
N.C.
N.C.
IEEE Std. 1149.1 BST Operation Control
Register
Cyclone III Device Handbook, Volume 1
Update
Drives
OE
Description
(2)
(2)
(2)
(2)
INJ
N.C.
N.C.
N.C.
N.C.
Register
Update
Input
(2)
(2)
(2)
(2)
PIN_IN
clock network or
logic array
PIN_IN
control logic
PIN_IN
configuration
control
OUTJ
output buffer
Comments
drives to
drives to
drives to
drives to
14–7