EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 118

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Figure 6–9. External Clock Outputs for PLLs
Notes to
(1)
(2)
6–18
Cyclone III Device Handbook, Volume 1
These external clock enable signals are available only when using the altclkctrl megafunction.
PLL#_CLKOUTp and PLL#_CLKOUTn pins are dual-purpose I/O pins that can be used as one single-ended or one
differential clock output.
Figure
6–9:
External Clock Outputs
Cyclone III PLLs each support one single-ended clock output (or one
differential pair). Only the c0 output counter can feed the dedicated
external clock outputs, as shown in
Each pin of a differential output pair is 180° out of phase. The Quartus II
software places the NOT gate in the design into the I/O element to
implement 180° phase with respect to the other pin in the pair. The clock
output pin pairs support the same I/O standards as standard output pins
(in the top and bottom banks) as well as LVDS, LVPECL, differential
HSTL, and differential SSTL.
PLL #
Notes
C0
C1
C2
C3
C4
clkena 0
(1),
PLL #_CLKOUTp
(2)
(1)
PLL #_CLKOUTn
(2)
Figure
Altera Corporation- Preliminary
6–9.
clkena 1
(2)
(1)
March 2007