EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 117

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EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
Datasheets

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Figure 6–8. Cyclone III PLL
Notes to
(1)
(2)
Altera Corporation-Preliminary
March 2007
pfdena
Cascade input
from another PLL
Clock inputs
from pins
GCLK
Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
This is the VCO post-scale counter, K.
Figure
4
6–8:
inclk0
inclk1
Switchover
Clock
Block
Notes
Figure 6–8
the Cyclone III PLL.
(1),
÷n
clkbad0
clkbad1
activeclock
clkswitch
(2)
shows a simplified block diagram of the major components of
PFD
LOCK
circuit
CP
lock
LF
VCO
Cyclone III Device Handbook, Volume 1
8
no compensation;
source-synch;
normal mode
÷2 (2)
ZDB mode
8
÷M
÷C0
÷C1
÷C2
÷C3
÷C4
output
PLL
mux
Cyclone III PLL
Casade output
to adjacent PLL
GCLKs
External clock
output
GCLK
networks
6–17

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