EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 126

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
6–26
Cyclone III Device Handbook, Volume 1
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on the PLL post-scale
counters. You can achieve the duty cycle setting by a low and high time
count setting for the post-scale counters. The Quartus II software uses the
frequency input and the required multiply or divide rate to determine the
duty cycle choices. The post-scale counter value determines the precision
of the duty cycle. The precision is defined by 50% divided by the post-
scale counter value. For example, if the C0 counter is 10, then steps of 5%
are possible for duty cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift
allows the generation of precise non-overlapping clocks.
PLL Control Signals
You can use the following three signals to observe and/or control the PLL
operation and resynchronization.
pfdena
Use the pfdena signal to maintain the last locked frequency so that your
system has time to store its current settings before shutting down. The
pfdena signal controls the PFD output with a programmable gate. If you
disable the PFD, the VCO operates at its last set value of control voltage
and frequency with some long-term drift to a lower frequency. The PLL
continues running even though it goes out of lock or the input clock is
disabled. You can use your own control signal or the control signals
available from the clock switchover circuit (activeclock, clkbad[0], or
clkbad[1]) to control pfdena.
areset
The areset signal is the reset or resynchronization input for each PLL.
The device input pins or internal logic can drive these input signals.
When driven high, the PLL counters reset, clearing the PLL output and
placing the PLL out of lock. The VCO is then set back to its nominal
setting. When driven low again, the PLL resynchronizes to its input as it
re-locks.
Altera Corporation- Preliminary
March 2007