EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 396

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
Guidelines for
IEEE Std. 1149.1
Boundary-Scan
Testing
14–22
Cyclone III Device Handbook, Volume 1
f
Use the following guidelines when performing boundary-scan testing
with IEEE Std. 1149.1 devices:
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■
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For more information on boundary scan testing, contact mySupport at
altera.com.
Note to
(1)
TMS
TCK
TDI
TDO
Table 14–6. Disabling IEEE Std. 1149.1 Circuitry
If the 10 bit checkerboard pattern (1010101010) does not shift out of
the instruction register via the TDO pin during the first clock cycle of
the SHIFT_IR state, the TAP controller did not reach the proper
state. To solve this problem, try one of the following procedures:
●
●
Perform a SAMPLE/PRELOAD test cycle prior to the first EXTEST test
cycle to ensure that known data is present at the device pins when
you enter the EXTEST mode. If the OEJ update register contains a 0,
the data in the OUTJ update register is driven out. The state must be
known and correct to avoid contention with other devices in the
system.
Do not perform EXTEST testing during ICR. This instruction is
supported before or after ICR, but not during ICR. Use the
CONFIG_IO instruction to interrupt configuration and then perform
testing, or wait for configuration to complete.
If performing testing before configuration, hold nCONFIG pin low.
There is no software option to disable JTAG in Cyclone III devices. The JTAG pins
are dedicated.
Table
Verify that the TAP controller has reached the SHIFT_IR state
correctly. To advance the TAP controller to the SHIFT_IR state,
return to the RESET state and send the code 01100 to the TMS
pin.
Check the connections to the V
configuration pins on the device.
JTAG Pins
14–6:
(1)
VCC
GND
VCC
Leave open
CC
Connection for Disabling
, GND, JTAG, and dedicated
Altera Corporation-Preliminary
March 2007