EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 7

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Contents
Chapter 5. Embedded Multipliers in Cyclone III Devices
Chapter 6. Clock Networks and PLLs in Cyclone III Devices
Altera Corporation
Conclusion ............................................................................................................................................ 4–32
Document Revision History ............................................................................................................... 4–32
Introduction ............................................................................................................................................ 5–1
Embedded Multiplier Block Overview .............................................................................................. 5–2
Architecture ............................................................................................................................................ 5–4
Operational Modes ................................................................................................................................ 5–7
Software Support ................................................................................................................................. 5–10
Conclusion ............................................................................................................................................ 5–11
Document Revision History ............................................................................................................... 5–11
Introduction ............................................................................................................................................ 6–1
Clock Networks ..................................................................................................................................... 6–1
PLLs in Cyclone III Devices ............................................................................................................... 6–13
Cyclone III PLL .................................................................................................................................... 6–16
Clock Feedback Modes ....................................................................................................................... 6–21
Hardware Features .............................................................................................................................. 6–24
Phase-Shift Implementation ............................................................................................................... 6–33
PLL Cascading ..................................................................................................................................... 6–35
PLL Reconfiguration ........................................................................................................................... 6–37
Spread-Spectrum Clocking ................................................................................................................ 6–47
PLL Specifications ................................................................................................................................ 6–47
Input Registers .................................................................................................................................. 5–5
Multiplier Stage ................................................................................................................................ 5–5
Output Registers ............................................................................................................................... 5–6
18-Bit Multipliers .............................................................................................................................. 5–7
9-Bit Multipliers ................................................................................................................................ 5–8
Global Clock Network ..................................................................................................................... 6–2
Clock Control Block ......................................................................................................................... 6–6
Global Clock Network Clock Source Generation ........................................................................ 6–8
Global Clock Network Power Down ........................................................................................... 6–10
Clkena Signals ................................................................................................................................. 6–11
Cyclone III PLL Hardware Overview ......................................................................................... 6–16
Cyclone III PLL Software Overview ............................................................................................ 6–19
Source-Synchronous Mode ........................................................................................................... 6–21
No Compensation Mode ............................................................................................................... 6–22
Normal Mode .................................................................................................................................. 6–23
Zero Delay Buffer (ZDB) Mode .................................................................................................... 6–23
Clock Multiplication and Division .............................................................................................. 6–24
Post-scale Counter Cascading ...................................................................................................... 6–25
Programmable Duty Cycle ........................................................................................................... 6–26
PLL Control Signals ....................................................................................................................... 6–26
Clock Switchover ............................................................................................................................ 6–27
Manual Override ............................................................................................................................ 6–30
PLL Reconfiguration Hardware Implementation ..................................................................... 6–37
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