EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 26

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device Family Overview
1–10
Cyclone III Device Handbook, Volume 1
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frequencies and corresponding multiplication, division, and phase shift
requirements. PLLs in Cyclone III devices may be cascaded to generate
up to 10 internal clocks and 2 external clocks on output pins from a single
external clock source.
For PLL specifications and information, please refer to the DC and
Switching Characteristics and Clock Networks and PLLs chapters in the
Cyclone III Device Handbook.
High-Speed Differential Interfaces
Cyclone III FPGAs support high-speed differential interfaces, such as
LVDS, mini-LVDS, RSDS, and PPDS. These high-speed I/O standards in
Cyclone III FPGAs are ideal for low-cost applications by providing high
data throughput using a relatively small number of I/O pins. All device
I/O banks contain LVDS receivers that operate at up to 875 Mbps data
rates. Dedicated differential output drivers on the left and right I/O
banks can transmit at up to 840 Mbps data rates without the need for any
external resistors to save board space and simplify PCB routing. Top and
bottom I/O banks support differential transmit functionality with the
addition of an external resistor network at up to 640 Mbps data rates.
For more information, refer to the High-Speed Differential Interfaces
chapter in the Cyclone III Device Handbook.
Auto-Calibrating External Memory Interfaces
Cyclone III devices support common memory types including DDR,
DDR2, SDR SDRAM, and QDRII SRAM. The DDR2 SDRAM memory
interfaces support data rates of up to 400 Mbps. Memory interfaces are
supported on all sides of the Cyclone III FPGA. The Cyclone III FPGA
contains features such as on-chip termination, DDR output registers, and
8- to 36-bit programmable DQ group widths to enable rapid and robust
implementation of different memory standards.
An auto-calibrating megafunction is available in the Quartus II software
for DDR and QDR memory interface PHYs. The megafunction is
optimized to take advantage of the Cyclone III I/O structure, simplify
timing closure requirements, and take advantage of the Cyclone III PLL
dynamic reconfiguration feature to calibrate over process, voltage and
temperature changes.
For more information, refer to the External Memory Interfaces chapter in
the Cyclone III Device Handbook.
Altera Corporation-Preliminary
March 2007