EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 212

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

High-Speed Differential Interfaces in Cyclone III Devices
Figure 8–24. Cyclone III High-Speed I/O Timing Budget
Note to
(1)
Design
Guidelines
8–22
Cyclone III Device Handbook, Volume 1
The equation for the high-speed I/O timing budget is: Period=0.5 x TCCS+RSKM+SW+RSKM+0.5 x TCCS.
Internal Clock Period
Figure
8–24:
f
f
See the Cyclone III Device Datasheet: DC and Switching Characteristics
chapter in volume 2 of the Cyclone III Device Handbook for more details.
This section provides guidelines for designing with Cyclone III devices.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the V
observe some restrictions on placement of single-ended I/O pins in
relation to differential pads.
Refer to the guidelines in the Cyclone III Device I/O Features chapter in
volume 1 of the Cyclone III Device Handbook for placing single-ended
pads with respect to differential pads in Cyclone III devices.
Board Design Considerations
This section explains how to get the optimal performance from the
Cyclone III I/O interface and ensure first-time success in implementing a
functional design with optimal signal quality. You must consider the
critical issues of controlled impedance of traces and connectors,
differential routing, and termination techniques to get the best
performance from the IC. Cyclone III devices generate signals that travel
over the media at frequencies as high as 840 Mbps.
0.5 × TCCS
RSKM
(1)
SW
Altera Corporation-Preliminary
CCIO
RSKM
supply, you must
0.5 × TCCS
March 2007