OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 89

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
9.6.15.1 Baud rate calculation
Table 105. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baud rate can be calculated as:
Where UART_PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART
baud rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the U0FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U0FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baud rate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
Bit
3:0
7:4
31:8
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL< MULVAL
Function
DIVADDVAL
MULVAL
-
UART
All information provided in this document is subject to legal disclaimers.
baudrate
Value Description
0
1
NA
Rev. 1 — 10 September 2010
Chapter 9: EM773 Universal Asynchronous Transmitter (UART)
=
Baud rate generation pre-scaler divisor value. If this field is
0, fractional baud rate generator will not impact the UART
baud rate.
Baud rate pre-scaler multiplier value. This field must be
greater or equal 1 for UART to operate properly,
regardless of whether the fractional baud rate generator is
used or not.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
----------------------------------------------------------------------------------------------------------------------------------
16
×
(
256
×
U0DLM
+
PCLK
U0DLL
)
×
⎛
⎝
1
+
DivAddVal
---------------------------- -
MulVal
UM10415
© NXP B.V. 2010. All rights reserved.
⎞
⎠
Reset
value
0
1
0
89 of 310
(3)