OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 172

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
Table 163: Capture Control Register (TMR32B0CCR - address 0x4001 4028) bit description
UM10415
User manual
Bit
0
1
2
31:3
Symbol
CAP0RE 1
CAP0FE
CAP0I
-
13.8.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
13.8.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001
13.8.8 Capture Control Register (TMR32B0CCR)
13.8.9 Capture Register (TMR32B0CR0 - address 0x4001 402C)
Value Description
0
1
0
1
0
4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Timer Counter when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0.
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM outputs” on page
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
This feature is disabled.
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
This feature is disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Chapter 13: EM773 32-bit counter/timers (CT32B0/1)
175).
(Section 13.8.13 “Rules for single edge
UM10415
© NXP B.V. 2010. All rights reserved.
172 of 310
Reset
value
0
0
0
NA