OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 169

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
Table 159. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000)
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Table 160: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
UM10415
User manual
Name
TMR32B1IR
TMR32B1TCR
TMR32B1TC
TMR32B1PR
TMR32B1PC
TMR32B1MCR
TMR32B1MR0
TMR32B1MR1
TMR32B1MR2
TMR32B1MR3
TMR32B1EMR
-
TMR32B1CTCR
TMR32B1PWMC R/W
Bit
0
1
2
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
description
Symbol
MR0 Interrupt
MR1 Interrupt
MR2 Interrupt
13.8.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
The Interrupt Register consists of four bits for the match interrupts and one bit for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x03C
0x040 -
0x06C
0x070
0x074
Address
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Description
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
Prescale Counter (PC). The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
Match Control Register (MCR). The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match occurs.
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
Match Register 1 (MR1). See MR0 description.
Match Register 2 (MR2). See MR0 description.
Match Register 3 (MR3). See MR0 description.
External Match Register (EMR). The EMR controls the match function
and the external match pins CT32B1_MAT[3:0].
reserved
Count Control Register (CTCR). The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
PWM Control Register (PWMCON). The PWMCON enables PWM
mode for the external match pins CT32B1_MAT[3:0].
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Chapter 13: EM773 32-bit counter/timers (CT32B0/1)
UM10415
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
0
Reset
value
0
0
0
0
0
0
0
0
0
0
0
-
0
0
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