OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 103

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
10.8.5.1 Selecting the appropriate I
10.8.5 I
Any of these registers which contain the bit 00x will be disabled and will not match any
address on the bus. The slave address register will be cleared to this disabled state on
reset. See also
Table 116. I
and I2C0SCLL- 0x4000 0014)
Table 117. I
Table 118. I
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of I2C_PCLK cycles for the SCL
HIGH time, I2SCLL defines the number of I2C_PCLK cycles for the SCL low time. The
frequency is determined by the following formula (I2C_PCLK is the frequency of the
peripheral I2C clock):
The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate
I
gives some examples of I
I2SCLH values.
Bit
0
7:1
31:8 -
Bit
15:0
31:16
Bit
15:0
31:16
2
2
C data rate range. Each register value must be greater than or equal to 4.
C SCL HIGH and LOW duty cycle registers (I2C0SCLH - 0x4000 0010
Symbol Description
GC
Address The I
Symbol
SCLH
-
Symbol
SCLL
-
description
2
2
2
C Slave Address register 0 (I2C0ADR0- 0x4000 000C) bit description
C SCL HIGH Duty Cycle register (I2C0SCLH - address 0x4000 0010) bit
C SCL Low duty cycle register (I2C0SCLL - 0x4000 0014) bit description
General Call enable bit.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Table
Description
Count for SCL HIGH time period selection.
Reserved. The value read from a reserved bit is not defined.
Description
Count for SCL low time period selection.
Reserved. The value read from a reserved bit is not defined.
2
C device address for slave mode.
Rev. 1 — 10 September 2010
122.
I 2 C
2
C-bus rates based on I2C_PCLK frequency and I2SCLL and
bitfrequency
2
C data rate and duty cycle
=
-------------------------------------------------------- -
I2CSCLH
I2CPCLK
Chapter 10: EM773 I2C-bus interface
+
I2CSCLL
UM10415
© NXP B.V. 2010. All rights reserved.
Reset value
0
0x00
-
Reset value
0x0004
-
Reset value
0x0004
-
Table 119
103 of 310
(4)