OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 151

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
Fig 33. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)
a. Single transfer with CPOL=1 and CPHA=0
b. Continuous transfer with CPOL=1 and CPHA=0
SSEL
MOSI
MISO
SCK
11.8.2.4 SPI format with CPOL = 1,CPHA = 0
MSB
MSB
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin
is enabled. After a further one half SCK period, both master and slave valid data is
enabled onto their respective transmission lines. At the same time, the SCK is enabled
with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line is
returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
Single and continuous transmission signal sequences for SPI format with CPOL=1,
CPHA=0 are shown in
In this configuration, during idle periods:
•
•
•
The CLK signal is forced HIGH.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
SSEL
MOSI
MISO
SCK
4 to 16 bits
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
MSB
LSB
Figure
LSB
MSB
Q
33.
4 to 16 bits
MSB
MSB
LSB
LSB
Chapter 11: EM773 SPI0 with SSP
Q
4 to 16 bits
UM10415
© NXP B.V. 2010. All rights reserved.
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Q
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