OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 32

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
3.7.2.3 Wake-up from Sleep mode
3.7.3.1 Power configuration in Deep-sleep mode
3.7.3.2 Programming Deep-sleep mode
3.7.3 Deep-sleep mode
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register.
Deep-sleep mode eliminates all power used by the flash and analog peripherals and all
dynamic power used by the processor itself, memory systems and related controllers, and
internal buses. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
Power consumption in Deep-sleep mode is determined by the Deep-sleep power
configuration setting in the PDSLEEPCFG
The following steps must be performed to enter Deep-sleep mode:
1. The DPDEN bit in the PCON register must be set to zero
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG
3. Select the power configuration after wake-up in the PDAWAKECFG
•
•
•
The only clock source available in Deep-sleep mode is the watchdog oscillator. The
watchdog oscillator can be left running in Deep-sleep mode if required for
timer-controlled wake-up (see
system oscillator) and the system PLL are shut down. The watchdog oscillator analog
output frequency must be set to the lowest value of its analog cock output (bits
FREQSEL in the WDTOSCCTRL = 0001, see
The BOD circuit can be left running in Deep-sleep mode if required by the application.
If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer or
one of the general-purpose timers should be enabled in SYSAHBCLKCTRL register
to minimize power consumption.
register.
a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is
b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down,
register.
powered in the PDRUNCFG register and switch the clock source to WD oscillator
in the MAINCLKSEL register
ensure that the IRC is powered in the PDRUNCFG register and switch the clock
source to IRC in the MAINCLKSEL register
system clock is shut down glitch-free.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Section
(Table
3.8.3). All other clock sources (the IRC and
(Table
14).
Chapter 3: EM773 System configuration
35) register:
Table
(Table
9).
14). This ensures that the
(Table
43).
UM10415
© NXP B.V. 2010. All rights reserved.
(Table
(Table
36)
32 of 13
35)