OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 104
OM13006,598
Manufacturer Part Number
OM13006,598
Description
BOARD EVAL EM773 METER EU PLUG
Manufacturer
NXP Semiconductors
Type
Other Power Managementr
Specifications of OM13006,598
Design Resources
Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
EM773FHN33,551
Interface Type
USB
Maximum Operating Temperature
+ 150 C
Operating Supply Voltage
1.8 V to 3.6 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
EM773, OL2381
Other names
568-6681
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NXP Semiconductors
UM10415
User manual
10.8.6 I
10.8.7 I
Table 119. I2SCLL + I2SCLH values for selected I
I2SCLL and I2SCLH values should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a Fast-mode
and Fast-mode Plus I
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 120. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the
I2CONSET register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
This register controls the Monitor mode which allows the I
the I
I
Standard mode
Fast-mode
Fast-mode Plus
Bit
1:0
2
3
4
5
6
7
31:8 -
2
2
2
C mode
C Control Clear register (I2C0CONCLR - 0x4000 0018)
C Monitor mode control register (I2C0MMCTRL - 0x4000 001C)
2
C bus without actually participating in traffic or interfering with the I
Symbol
-
AAC
SIC
-
STAC
I2ENC
-
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
C Control Clear register (I2C0CONCLR - 0x4000 0018) bit description
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Reserved. The value read from a reserved bit is not defined.
2
2
2
C interrupt Clear bit.
C interface Disable bit.
1 MHz
I
frequency
100 kHz
400 kHz
C interface. Writing a one to a bit of this register causes the
2
C bit
Rev. 1 — 10 September 2010
2
C.
2
C control register to be cleared. Writing a zero has no effect.
6
60
15
-
8
80
20
8
100
25
10
10
2
C clock values
120
30
12
12
Chapter 10: EM773 I2C-bus interface
I2SCLH + I2SCLL
I2C_PCLK (MHz)
16
160
40
16
2
C module to monitor traffic on
20
200
50
20
30
300
75
30
UM10415
© NXP B.V. 2010. All rights reserved.
2
C bus.
40
400
100
40
2
C-bus
Reset
value
NA
0
NA
0
0
NA
-
104 of 310
50
500
125
50
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