OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 84

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
9.6.10 UART Modem Status Register
Table 101. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
The U0MSR is a read-only register that provides status information on the modem input
signals. U0MSR[3:0] is cleared on U0MSR read. Note that modem signals have no direct
effect on the UART operation. They facilitate the software implementation of modem
signal operations.
Bit Symbol
3
4
5
6
7
31:
8
Framing
Error
Break
Interrupt
Transmitter
Holding
Register
Empty
Transmitter
Empty
(TEMT)
Error in RX
FIFO
(RXFE)
-
(FE)
(BI)
(THRE)
description
All information provided in this document is subject to legal disclaimers.
Value Description
-
0
1
0
1
0
1
0
1
0
1
Rev. 1 — 10 September 2010
Chapter 9: EM773 Universal Asynchronous Transmitter (UART)
…continued
When the stop bit of a received character is a logic 0, a framing
error occurs. A U0LSR read clears U0LSR[3]. The time of the
framing error detection is dependent on U0FCR0. Upon
detection of a framing error, the RX will attempt to
re-synchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no Framing
Error.
Note: A framing error is associated with the character at the top
of the UART RBR FIFO.
Framing error status is inactive.
Framing error status is active.
When RXD1 is held in the spacing state (all zeros) for one full
character transmission (start, data, parity, stop), a break
interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXD1 goes to marking state (all
ones). A U0LSR read clears this status bit. The time of break
detection is dependent on U0FCR[0].
Note: The break interrupt is associated with the character at the
top of the UART RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
THRE is set immediately upon detection of an empty UART
THR and is cleared on a U0THR write.
U0THR contains valid data.
U0THR is empty.
TEMT is set when both U0THR and U0TSR are empty; TEMT is
cleared when either the U0TSR or the U0THR contain valid
data.
U0THR and/or the U0TSR contains valid data.
U0THR and the U0TSR are empty.
U0LSR[7] is set when a character with a RX error such as
framing error, parity error or break interrupt, is loaded into the
U0RBR. This bit is cleared when the U0LSR register is read
and there are no subsequent errors in the UART FIFO.
U0RBR contains no UART RX errors or U0FCR[0]=0.
UART RBR contains at least one UART RX error.
Reserved
UM10415
© NXP B.V. 2010. All rights reserved.
84 of 310
Reset
Value
0
0
1
1
0
-