OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 263
OM13006,598
Manufacturer Part Number
OM13006,598
Description
BOARD EVAL EM773 METER EU PLUG
Manufacturer
NXP Semiconductors
Type
Other Power Managementr
Specifications of OM13006,598
Design Resources
Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
EM773FHN33,551
Interface Type
USB
Maximum Operating Temperature
+ 150 C
Operating Supply Voltage
1.8 V to 3.6 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
EM773, OL2381
Other names
568-6681
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NXP Semiconductors
UM10415
User manual
20.4.5.3.2 Operation
20.4.5.3.3 Restrictions
20.4.5.3.4 Condition flags
20.4.5.3.5 Examples
20.4.5.4 CMP and CMN
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
where:
The range of shift length depends on the instruction:
ASR — shift length from 1 to 32
LSL — shift length from 0 to 31
LSR — shift length from 1 to 32.
Remark: MOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.
ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left,
logical-shift-right or a right-rotation of the bits in the register Rm by the number of places
specified by the immediate imm or the value in the least-significant byte of the register
specified by Rs.
For details on what result is generated by the different instructions, see
Section
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register.
These instructions update the N and Z flags according to the result.
The C flag is updated to the last bit shifted out, except when the shift length is 0, see
Section
Compare and Compare Negative.
Rd is the destination register. If Rd is omitted, it is assumed to take the same value as
Rm.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm.
imm is the shift length.
ASRS
20–20.4.3.3.
20–20.4.3.3. The V flag is left unmodified.
LSLS
LSRS
RORS
R7, R5, #9 ; Arithmetic shift right by 9 bits
All information provided in this document is subject to legal disclaimers.
R1, R2, #3 ; Logical shift left by 3 bits with flag update
R4, R5, #6 ; Logical shift right by 6 bits
R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.
Rev. 1 — 10 September 2010
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
UM10415
© NXP B.V. 2010. All rights reserved.
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