LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 373

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
IN_DEL
ROUTE
MCLK_DEL
ROUTE
OUTREG_DEL
IN_DEL
ROUTE
MCLK_DEL
ROUTE
OUTDD_DEL
NCLK_DEL
ROUTE
Report:
===========================================================================
Constraint Details:
Physical Path Details:
Data Path Delay:
Clock Path Delay:
Name
Name
Name
Name
3.171ns delay clk to ddr_cas_n less
1.905ns feedback compensation
0.928ns delay ddr_cas_n to ddr_cas_n less
1.138ns delay clk to ddr_clk (totaling 1.056ns) meets
0.000ns hold offset clk to ddr_cas_n by 1.056ns
Clock path clk to ddr_cas_n:
Data path ddr_cas_n to ddr_cas_n:
Clock out path:
Feedback path:
Fanout
Fanout
Fanout
Fanout
1.056ns is the maximum offset for this preference.
---
---
449
---
---
---
449
---
---
136
1
1
--------
--------
--------
--------
Delay (ns)
0.576
0.507
0.231
1.857
3.171
Delay (ns)
0.928
0.928
Delay (ns)
0.576
0.507
0.231
0.778
0.951
3.043
Delay (ns)
0.231
1.674
1.905
0.928ns
3.171ns
LLHPPLL.CLKIN to
LLHPPLL.CLKIN to
LLHPPLL.CLKIN to
LLHPPLL.MCLK to
(25.4% logic, 74.6% route), 2 logic levels.
(100.0% logic, 0.0% route), 1 logic levels.
LLHPPLL.MCLK to
(57.8% logic, 42.2% route), 3 logic levels.
LLHPPLL.NCLK to
(12.1% logic, 87.9% route), 1 logic levels.
AF3.OUTDD to
AB4.INCK to
AB4.INCK to
(100.0% logic, 0.0% route), 1 logic levels.
(25.4% logic, 74.6% route), 2 logic levels.
AB4.PAD to
AE15.SC to
AB4.PAD to
Site
Site
Site
Site
18-13
LLHPPLL.CLKIN clk_c
LLHPPLL.CLKIN clk_c
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
AF3.OUTDD ddr_clk_c
AB4.INCK clk
AE15.PAD ddr_cas_n (from ddr_clk_c)
AB4.INCK clk
AE15.SC ddr_clk_c
AF3.PAD ddr_clk
for the DDR SDRAM Controller IP Core
Resource
Resource
Resource
Resource
Board Timing Guidelines