LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 250

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Verilog Example
module ddrin (rst, ddrclk, ddrdata, datap, datan)/*synthesis syn_useioff = 0*/;
// Inputs
input
input
input
// Outputs
output
reg [7:0] pos0/*synthesis syn_keep=1*/;
reg [7:0] pos1/*synthesis syn_keep=1*/;
reg [7:0] neg0/*synthesis syn_keep=1*/;
reg [7:0] datap, datan/*synthesis syn_keep=1*/;
//PLL signals
wire ddrclk0;
wire ddrclk90;
pll I0 (.CLK(ddrclk), .RESET(rst), .CLKOP(ddrclk0), .CLKOS(ddrclk90), .LOCK(clklock));
always @ ( posedge ddrclk90)
begin
end
always@ (negedge ddrclk90)
begin
end
always @ (posedge ddrclk90)
begin
if (rst)
begin
pos0 <= 0;
end
else
begin
end
if (rst)
begin
end
else
begin
end
if (rst)
begin
end
else
begin
end
pos0 <= ddrdata;
neg0<=0;
pos1<=0;
neg0<=ddrdata;
pos1<=pos0;
datap<= 0;
datan<= 0;
datap<= pos1;
datan<= neg0;
[7:0]
[7:0]
rst;
ddrclk;
ddrdata;
datap, datan;
10-31
LatticeECP/EC and LatticeXP
DDR Usage Guide