LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 300

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeXP sysCONFIG
Usage Guide
September 2008
Technical Note TN1082
Introduction
The memory in the LatticeXP™ FPGAs is built using Flash cells, along with SRAM cells, so that configuration
memory can be loaded automatically at power-up, or at any time the user wishes to update the device. In addition
to “instant-on” capability, on-chip Flash memory greatly increases design security by getting rid of the external con-
figuration bitstream; while maintaining the ease of use and reprogrammability of an SRAM-based FPGA.
While an external device is not required, the LatticeXP does support several external configuration modes. The
available external configuration modes are:
• Slave Serial
• Master Serial
• Slave Parallel
• ispJTAG™ (1149.1 interface)
This guide will cover all the configuration options available for the LatticeXP.
Programming Overview
The LatticeXP contains two types of memory, SRAM and Flash (refer to Figure 13-1). SRAM contains the FPGA
configuration, essentially the “fuses” that define the circuit connections; Flash provides an internal storage space
for the configuration data.
The SRAM can be configured using JTAG, one of the external configuration modes, or by using the data stored in
on-chip Flash. The configuration process consists of SRAM initialization (clear the RAM and the address pointers),
loading the SRAM with the configuration data, and setting the FPGA into user mode (waking up the FPGA).
On-chip Flash can be programmed by using JTAG or by using the external Slave Parallel port. JTAG Flash pro-
gramming can be performed any time the device is powered up. The Slave Parallel port uses the sysCONFIG™
pins and can program the Flash directly or in the background. Direct programming takes place during config mode,
background programming during user mode. The FPGA enters config mode at power up, when the PROGRAMN
pin is pulled low, or when a refresh command is issued via JTAG; it enters user mode when it wakes up, i.e. when
the device begins running user code. These two programming modes, direct and background, will be referred to in
this document as Flash Direct and Flash Background.
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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