LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 201
![FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I](/photos/16/2/160258/tqfp-100_sml.jpg)
LFXP3C-3TN100I
Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP3C-3TN100I
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 9-40. FIFO with Output Registers, End of Data Read Cycle
And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle
(as compared to the non-pipelined FIFO), and the RdEn should be high also during that clock cycle, otherwise the
data takes an extra clock cycle when the RdEn goes true.
Figure 9-41. FIFO with Output Registers and RdEn on Output Registers
Almost Full
Almost
Almost
Empty
Empty
Almost
Reset
Clock
WrEn
RdEn
Reset
Empty
Empty
Clock
WrEn
RdEn
Data
Data
Full
Full
Full
Q
Q
Invalid Data
Data_N-5
Data_1
Data_N-4
Data_2
Invalid Data
Data_N-3
9-36
Invalid Data
Data_3
Data_N-2
LatticeECP/EC and LatticeXP Devices
Data_4
Data_N-1
Data_1
Data_5
Memory Usage Guide
Data_N
Data_2
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