LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 320

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice ispTRACY Usage Guide
Once IPexpress is launched, you will be presented with the option of generating the ispTRACY IP module by
selecting the JTAG module uner Architecture and clicking the Customize button. Figure 14-2 shows the IPexpress
window. Selections for the project path and module name are made through this window
Figure 14-2. ispTRACY IP Manager Program Window
ispTRACY Core Generator
The ispTRACY Core Generator under JTAG Module provides all the controls for customizing the ispTRACY
core(s). Selections on this page influence the final size of the core(s) inside the FPGA and features available in
terms of triggers, size of data bus and depth of memory capture. Figure 14-3 shows the Core Generator window
and Table 14-3 contains descriptions of each of the figures available in the IP core. Once the core features are
selected, clicking on the Generate button will create the necessary files for the Core Linker Program.
Figure 14-3. ispTRACY Core Generator Window
14-2