LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 264

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-6. IPexpress Main Window
Configuration Tab
The Configuration Tab lists all user accessible attributes. Default values are set initially.
There are two modes in the Configuration Tab which can be used to configure the PLL, Frequency Mode and
Divider Mode.
Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the
divider settings for the user. If the output frequency the user entered is not achievable, the nearest frequency will be
displayed in the ‘Actual’ text box. After input and output frequencies are entered, clicking the ‘Calculate’ button will
display the divider values. If the desired output frequency is not achievable with the given frequency tolerance, the
software generates an error. Users may increase the frequency tolerance or change the output frequencies.
Figure 11-7 shows the Configuration Tab window.
11-8