LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 210

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 9-14. PFU based Distributed Single port RAM Port Definitions
Users have an option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-
ures 8-35 and 8-36 show the internal timing waveforms for the Distributed Single Port RAM (Distributed_SPRAM)
with these options.
Figure 9-53. PFU Based Distributed Single Port RAM Timing Waveform - Without Output Registers
ClockEn
Address
Clock
Data
Clock
ClockEn
Reset
WE
Address
Data
Q
WE
Q
Generated Module
Port Name in
t
t
SUWREN_PFU
SUADDR_PFU
t
SUDATA_PFU
Data_0
Add_0
Invalid Data
CK
-
-
WRE
AD[3:0]
DI[1:0]
DO[1:0]
Port Name in the EBR
t
t
HADDR_PFU
HDATA_PFU
Block Primitive
Data_1
Add_1
t
HWREN_PFU
t
CORAM_PFU
9-45
Clock
Clock Enable
Reset
Write Enable
Address
Data In
Data Out
Add_0
Description
LatticeECP/EC and LatticeXP Devices
Data_0
Add_1
Data_1
Rising Clock Edge
Active High
Active High
Active High
—
—
—
Memory Usage Guide
Active State
Add_2
Data_2