LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 262
![FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I](/photos/16/2/160258/tqfp-100_sml.jpg)
LFXP3C-3TN100I
Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP3C-3TN100I
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Dynamic Delay Adjustment
The Dynamic Delay Adjustment is controlled by the DDAMODE input. When the DDAMODE input is set to “1”, the
delay control is handled through the inputs, DDAIZR, DDAILAG and DDAIDEL(2:0). For this mode, the attribute
“DELAY_CNTL” must be set to “DYNAMIC”. Table 11-3 shows the delay adjustment values based on the attri-
bute/input settings.
In this mode, the PLL may come out of lock due to the abrupt change of phase. RST must be asserted to re-lock
the PLL. Upon de-assertion of RST, the PLL will start the lock-in process and will take the t
the PLL lock.
Figure 11-4. Pre-Map Preference Editor
4. EPIC Device Editor: Users can edit their preferences in the EPIC Device Editor as shown in Figure 11-5.
Figure 11-5. EPIC Preferences Edit Window
11-6
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
LOCK
time to complete
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