LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 139
![FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I](/photos/16/2/160258/tqfp-100_sml.jpg)
LFXP3C-3TN100I
Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP3C-3TN100I
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
September 2005
September 2005
December 2005
December 2006
November 2007
February 2006
February 2007
August 2006
March 2006
March 2006
June 2006
April 2006
May 2006
July 2007
(cont.)
Date
Version
(cont.)
03.0
03.1
04.0
04.1
04.2
04.3
04.4
04.5
04.6
04.7
04.8
04.9
05.0
05.1
Characteristics (cont.)
Ordering Information
Pinout Information
Pinout Information
Pinout Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
DC and Switching
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Characteristics
Characteristics
Characteristics
Characteristics
Supplemental
Supplemental
Architecture
Architecture
Architecture
Introduction
Architecture
Architecture
Introduction
Information
Information
Section
Updated Typical Building Block Function Performance timing numbers.
Updated External Switching Characteristics timing numbers.
Updated Internal Timing Parameters.
Updated LatticeXP Family timing adders.
Updated LatticeXP "C" Sleep Mode timing numbers.
Updated JTAG Port Timing numbers.
Added clarification to SLEEPN and TOE description.
Clarification of dedicated LVDS outputs.
Updated list of technical notes.
Power Supply and NC Connections table corrected VCCP1 pin number
for 208 PQFP.
Moved data sheet from Advance to Final.
Added clarification to Typical I/O Behavior During Power-up section.
Added clarification to Recommended Operating Conditions.
Updated timing numbers.
Updated Signal Descriptions table.
Added clarification to Differential I/O Per Bank.
Updated Differential dedicated LVDS output support.
Added 208 PQFP lead-free package and ordering part numbers.
Corrected description of Signal Names VREF1(x) and VREF2(x).
Corrected condition for IIL and IIH.
Added clarification to Recommended Operating Conditions for
VCCAUX.
Removed Bank designator "5" from SLEEPN/TOE ball function.
Added footnote 2 regarding threshold level for PROGRAMN to sysCON-
FIG Port Timing Specifications table.
Corrected LVDS25E Output Termination Example.
Added clarification to Typical I/O Behavior During Power-Up section.
Added clarification to Left and Right sysIO Buffer Pair section.
Changes to LVDS25E Output Termination Example diagram.
EBR Asynchronous Reset section added.
Updated EBR Asynchronous Reset section.
Updated LatticeXP Family Selection Guide table.
Updated Typical I/O Behavior During Power-up text section.
Updated sysIO Single-Ended DC Electrical Characteristics table. Split
out LVCMOS 1.2 by supply voltage.
Added JTAG Port Timing Waveforms diagram.
Added Thermal Management text section.
Updated title list.
7-2
Change Summary
LatticeXP Family Data Sheet
Revision History
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