LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 333

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Initialization and Default State
A state machine must be initialized to a valid state after power-up. This can be done at the device level during
power up or by including a reset operation to bring it to a known state. For all Lattice Semiconductor FPGA devices,
the Global Set/Reset (GSR) is pulsed at power-up, regardless of the function defined in the design source code. In
the above example, an asynchronous reset can be used to bring the state machine to a valid initialization state. In
the same manner, a state machine should have a default state to ensure the state machine will not go into an
invalid state if not all the possible combinations are clearly defined in the design source code. VHDL and Verilog
have different syntax for default state declaration. In VHDL, if a CASE statement is used to construct a state
machine, “When Others” should be used as the last statement before the end of the statement, If an IF-THEN-
ELSE statement is used, “Else” should be the last assignment for the state machine. In Verilog, use “default” as the
last assignment for a CASE statement, and use “Else” for the IF-THEN-ELSE statement.
Full Case and Parallel Case Specification in Verilog
Verilog has additional attributes to define the default states without writing it specifically in the code. One can use
“full_case” to achieve the same performance as “default”. The following examples show the equivalent representa-
tions of the same code in Synplify. LeonardoSpectrum allows users to apply Verilog-specific options in the GUI set-
tings.
“Parallel_case” makes sure that all the statements in a case statement are mutually exclusive. It is used to inform
the synthesis tools that only one case can be true at a time. The syntax for this attribute in Synplify is as follows:
Using Pipelines in the Designs
Pipelining can improve design performance by restructuring a long data path with several levels of logic and break-
ing it up over multiple clock cycles. This method allows a faster clock cycle by relaxing the clock-to-output and
setup time requirements between the registers. It is usually an advantageous structure for creating faster data
paths in register-rich FPGA devices. Knowledge of each FPGA architecture helps in planning pipelines at the
// synthesis parallel_case
...
architecture lattice_fpga of FSM1 is
begin
process(clk, rst)
begin
end process;
...
…
case (current_state)
…
type state_typ is (deflt, idle, read, write);
signal next_state : state_typ;
if (rst='1') then
elsif (clk'event and clk='1') then
end if;
2’b00 : next_state <= 2’b01;
2’b01 : next_state <= 2’b11;
2’b11 : next_state <= 2’b00;
next_state <= idle; dout <= '0';
case next_state is
end case;
when idle =>
when read =>
when write =>
when others =>
next_state <= read; dout <= din(0);
next_state <= write; dout <= din(1);
next_state <= idle; dout <= din(2);
next_state <= deflt; dout <= '0';
When Others in VHDL
// synthesis full_case
13-6
...
// Define state labels explicitly
parameter deflt=2'bxx;
parameter idle =2'b00;
parameter read =2'b01;
parameter write=2'b10;
reg [1:0] next_state;
reg dout;
always @(posedge clk or posedge rst)
if (rst) begin
end
else begin
…
case (current_state)
next_state <= idle;
dout <= 1'b0;
case(next_state)
2’b00 : next_state <= 2’b01;
2’b01 : next_state <= 2’b11;
2’b11 : next_state <= 2’b00;
default : next_state <= 2bx;
idle: begin
read: begin
write: begin
default: begin
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
end
end
end
Default Clause in Verilog
dout <= din[0]; next_state <= read;
dout <= din[1]; next_state <= write;
dout <= din[2]; next_state <= idle;
end
dout <= 1'b0; next_state <= deflt;