LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 174

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The Single Port RAM (RAM_DQ) can be configured as NORMAL, READ BEFORE WRITE or WRITE THROUGH
modes. Each of these modes affects what data comes out of the port Q of the memory during the write operation
followed by the read operation at the same memory location. The READ BEFORE WRITE attribute is supported for
x9, x18 and x36 data widths.
Additionally users can select to enable the output registers for RAM_DQ. Figures 8-7 through 8-12 show the inter-
nal timing waveforms for the Single Port RAM (RAM_DQ) with these options.
Figure 9-9. Single Port RAM Timing Waveform – NORMAL Mode, without Output Registers
ClockEn
Address
Clock
WrEn
Data
Q
t
t
SUADDR_EBR
SUDATA_EBR
t
SUCE_EBR
Data_0
Add_0
t
SUWREN_EBR
t
t
HADDR_EBR
HDATA_EBR
Invalid Data
Data_1
Add_1
t
HWREN_EBR
9-9
Add_0
LatticeECP/EC and LatticeXP Devices
t
CO_EBR
Data_0
Add_1
Memory Usage Guide
Data_1
Add_2
t
HCE_EBR
Data_2