LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 270

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFEC6/LFXP6 and smaller devices have limited routing resources and can implement a maximum of nine second-
ary clocks per device.
Figure 11-11. Primary Clock and Secondary Clock/CE/LSR Distribution
Dynamic Clock Selection (DCS)
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock
sources and avoids glitches or runt pulses on the output clock, regardless of when the enable signal is toggled. The
DCS blocks are located in pairs at the center of each side of the device. Thus, there are eight of them in every
device.
Table 11-5. DCS I/O
Primary Clock Net
Secondary Clock/CE/LSR Net
Input
Output
PCLK0
PCLK1
PCLK2
PCLK3
SCLK0/CE/LSR
SCLK1/CE/LSR
SCLK2/CE/LSR
SCLK3/CE/LSR
I/O
SEL
CLK0
CLK1
DCSOUT
Name
Primary Clock
11-14
Secondary Clock
Secondary Clock
Secondary Clock
Input Clock Select
Primary Clock Input 0
Primary Clock Input 1
To Primary Clock
Local
Local
/CE/LSR
/CE/LSR
/CE/LSR
sysCLOCK PLL Design and Usage Guide
Local
3
4
Description
3
3
LatticeECP/EC and LatticeXP
CLK(0:3)
CE(0:3)
LSR(0:3)
PFU
PFU
PFU