LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 204

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-43. FIFO_DC Without Output Registers, End of Data Write Cycle
In this case, the Almost Full flag is in location 2 before the FIFO_DC is filled. The Almost Full flag is asserted when
N-2 location is written, and Full flag is asserted when the last word is written into the FIFO_DC.
Data_X data inputs do not get written as the FIFO_DC is full (Full flag is high).
Note that the assertion of these flags is immediate and there is no latency when they go true.
Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 9-44 shows the start of
the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags get de-asserted as shown.
In this case, note that the de-assertion is delayed by two clock cycles.
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Data_N-2
Data_N-1
9-39
Invalid Q
Data_N
LatticeECP/EC and LatticeXP Devices
Data_X
Data_X
Memory Usage Guide