LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 246

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
--***************************************************************************************
--*****TRISTATE Instantiations***********************************************************
-- DDR Trisate for data, DQ
--DDR Trisate for strobe, DQS
--****************************************************************************************
--***************DDR Output***************************************************************
--DQ OUTPUT
I8 : IDDRXB PORT MAP(D=> ddrin(6), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
I9 : IDDRXB PORT MAP(D=> ddrin(7), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
T0 : ODDRXB PORT MAP( DA => datatri_p(0), DB => datatri_n(0), LSR => reset,
T1 : ODDRXB PORT MAP( DA => datatri_p(1), DB => datatri_n(1), LSR => reset,
T2 : ODDRXB PORT MAP( DA=>
T3 : ODDRXB PORT MAP( DA => datatri_p(3), DB => datatri_n(3), LSR => reset,
T4 : ODDRXB PORT MAP( DA => datatri_p(4), DB => datatri_n(4), LSR => reset,
T5 : ODDRXB PORT MAP( DA => datatri_p(5), DB => datatri_n(5), LSR => reset,
T6 : ODDRXB PORT MAP( DA => datatri_p(6), DB => datatri_n(6), LSR => reset,
T7 : ODDRXB PORT MAP( DA => datatri_p(7), DB => datatri_n(7), LSR => reset,
T8: ODDRXB PORT MAP( DA =>dqstri_p, DB=> dqstri_n, LSR=> reset, CLK=> clk90,
O0 : ODDRXB PORT MAP( DA => dataout_p(0), DB
O1 : ODDRXB PORT MAP( DA => dataout_p(1), DB
O2 : ODDRXB PORT MAP( DA => dataout_p(2), DB
O3 : ODDRXB PORT MAP( DA => dataout_p(3), DB
O4 : ODDRXB PORT MAP( DA => dataout_p(4), DB
O5 : ODDRXB PORT MAP( DA => dataout_p(5), DB
O6 : ODDRXB PORT MAP( DA => dataout_p(6), DB
O7 : ODDRXB PORT MAP( DA => dataout_p(7), DB
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(6),
QB => datain_n(6));
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(7),
QB => datain_n(7));
CLK => clkinv, Q => tridata(0));
CLK => clkinv, Q => tridata(1));
CLK => clkinv, Q => tridata(2));
CLK => clkinv, Q => tridata(3));
CLK => clkinv, Q => tridata(4));
CLK => clkinv, Q => tridata(5));
CLK => clkinv, Q => tridata(6));
CLK => clkinv, Q => tridata(7));
Q => tridqs);
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
=> clkinv, Q => ddrout(0));
=> clkinv, Q => ddrout(1));
=> clkinv, Q => ddrout(2));
=> clkinv, Q => ddrout(3));
=> clkinv, Q => ddrout(4));
=> clkinv, Q => ddrout(5));
=> clkinv, Q => ddrout(6));
=> clkinv, Q => ddrout(7));
datatri_p(2), DB => datatri_n(2), LSR => reset,
10-27
=> dataout_n(0), LSR => reset,
=> dataout_n(1), LSR => reset,
=> dataout_n(2), LSR => reset,
=> dataout_n(3), LSR => reset,
=> dataout_n(4), LSR => reset,
=> dataout_n(5), LSR => reset,
=> dataout_n(6), LSR => reset,
=> dataout_n(7), LSR => reset,
LatticeECP/EC and LatticeXP
DDR Usage Guide