LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 318
![FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I](/photos/16/2/160258/tqfp-100_sml.jpg)
LFXP3C-3TN100I
Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP3C-3TN100I
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 318 of 397
- Download datasheet (10Mb)
Lattice Semiconductor
VHDL:
u1: STRTUP port map (UCLK =><clock name>);
INBUF
The I/O INBUF option will disable all unused input buffers to save power. INBUF mode limits some of the function-
ality of Boundary Scan. For Boundary Scan testing it is recommended that the I/O Power Save mode be set to ON
so that all of the I/Os will be fully functional.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet: www.latticesemi.com
Revision History
component STRTUP
end component;
attribute syn_noprune: boolean ;
attribute syn_noprune of STRTUP: component is true;
begin
September 2005
September 2007
September 2008
February 2005
February 2006
August 2007
March 2005
March 2008
July 2005
July 2008
port(STRTUP: in STD_ULOGIC );
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
Date
Version
01.0
01.1
01.2
01.3
01.4
01.5
01.6
01.7
01.8
01.9
Initial release.
Changed Figure 12-1 to make it more understandable
Changed Table 12-5 to make it more understandable
Changed CFG[0:1] to CFG[1:0]
Added msb, lsb references to D[0:7]
Added Max Config Bits Table
Changed INITN description, INITN is low during SDM configuration
Added information on how to use the sysCONFIG dual-purpose pins as
GPIO.
Removed "pull-up" from TDO signal.
Nomenclature for Power Save feature changed to INBUF.
Updated Dual-Purpose sysCONFIG Pins text section.
Updated PROGRAMN text section.
Updated CSN and SC1N text section.
Updated Bypass Overflow Option text section.
Updated Flow-Through Overflow Option text section.
Updated Slave Parallel Mode text section.
Updated LatticeXP Device Preference List table.
Updated Wake-Up Sequence to Internal Clock waveform.
Replaced Wake-up Clock Selection text section with new Start_Up
Clock Selection text section.
Updated CCLK text section.
13-19
LatticeXP sysCONFIG Usage Guide
Change Summary
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