LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 361

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

June 2004
Introduction
This document describes how to meet board timing requirements for DDR signals. The Lattice DDR SDRAM Con-
troller IP core, non-pipelined version (DDR-NP) is used as an example.
Figure 18-1 describes the timing diagram for the DDR signals. A total of five clocks are used in the DDR board
design using the Lattice DDR IP core. The following is the clock description:
clk:
ddr_clk:
ddr_clk_n:
pll_mclk (clkx):
pll_nclk (clk2x): A 266MHz clock for DDR NP, used inside the FPGA only.
Figure 18-1. DDR Signal Timing Diagram
www.latticesemi.com
CLK
CLKIN
CLKFB
Input clock for PLL (max. frequency of 133MHz for DDR NP)
Output clock going to DDR (max. frequency of 133MHz for DDR NP)
Negated version of ddr_clk
Same as ddr_clk, used inside the FPGA only.
PLL
CLK2X
CLKX
t
FPGA_CLK
pll_nclk
pll_mclk
t
CDQ
t
DDR_CLK
t
t
CCTRL
CDQS
Board Timing Guidelines for the
DDR SDRAM Controller IP Core
clk2x tree
FPGA
18-1
clkx tree
FPGA
ddr_dq_in
(read flops)
ddr_dq_out
(write flops)
D
D
Q
D
D
Q
Q
Q
D
Q
t
ENB
PD
ddr_dq
ddr_ad &
command signals
ddr_clk
ddr_clk_n
dqs_out
t
BDCTRL
t
BDC
t
t
BDDS
BDD
Technical Note TN1071
MEMORY
DDR
tn1071_01.0