LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 170

• Manufacturer Part Number: LFXP3C-3TN100I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LFXP3C-3TN100I

• Number Of Programmable I/os: 62
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-100
• Package: 100TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 62
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-5. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress
In the right-hand pane, options like Macro Type, Version, and Module_Name are device and selected module
dependent. These cannot be changed in IPexpress.
Users can change the directory where the generated module files will be placed by clicking the browse button in
the Project Path.
The File Name text box allows users to specify the entity and file name for the module they are about to generate.
Users must provide this name.
Design Entry, Verilog or VHDL, by default is the same as the project type. If the project is a VHDL project, the
selected Design Entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-
HDL.
Then click the Customize button. This opens another window where the RAM can be customized.
The the left-hand side of this window shows the block diagram of the module. The right-hand side includes the
Configuration tab.
9-5