EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 51

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.3.5 Memory scatter-gather
2010-12-21 - d0034_Rev0.90
and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA
transaction completes.
Note
In memory scatter-gather mode the controller receives an initial request and then performs four DMA
transfers using the primary data structure. After this transfer completes, it starts a DMA cycle using the
alternate data structure. After this cycle completes, the controller performs another four DMA transfers
using the primary data structure. The controller continues to switch from primary to alternate to primary…
until either:
• the host processor configures the alternate data structure for a basic cycle
• it reads an invalid data structure.
The controller only asserts dma_done[C] when the scatter-gather transaction completes using an auto-
request cycle.
In scatter-gather mode, the controller uses the primary data structure to program the alternate data
structure. Table 8.4 (p. 51) lists the fields of the channel_cfg memory location for the primary data
structure, that you must program with constant values and those that can be user defined.
Table 8.4. channel_cfg for a primary data structure, in memory scatter-gather mode
1
that you must configure the alternate data structure.
See Section 8.4.3.3 (p. 58) for more information.
Figure 8.4 (p. 52) shows a memory scatter-gather example.
Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times
Bit
Constant-value fields:
[31:30}
[29:28]
[27:26]
[25:24]
[17:14]
[3]
[2:0]
User defined values:
[23:21]
[20:18]
[13:4]
Note
Field
dst_inc
dst_size
src_inc
src_size
R_power
next_useburst
cycle_ctrl
dst_prot_ctrl
src_prot_ctrl
n_minus_1
You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 49) , if you configure
task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.
After the controller completes the N primary transfers it invalidates the primary data
structure by setting the cycle_ctrl field to b000.
Value
b10
b10
b10
b10
b0010
0
b100
-
-
N
1
Description
Configures the controller to use word increments for the address
Configures the controller to use word transfers
Configures the controller to use word increments for the address
Configures the controller to use word transfers
Configures the controller to perform four DMA transfers
For a memory scatter-gather DMA cycle, this bit must be set to zero
Configures the controller to perform a memory scatter-gather DMA cycle
Configures the state of HPROT when the controller writes the destination data
Configures the state of HPROT when the controller reads the source data
Configures the controller to perform N DMA transfers, where N is a multiple of four
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