EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 241

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.17 LEUARTn_FREEZE - Freeze Register
16.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
31:6
5
4
3:0
31:1
0
31:8
7
Bit
Offset
0x040
Reset
Access
Name
Bit
Offset
0x044
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
PULSEFILT
Enable a one-cycle pulse filter for pulse extender
PULSEEN
Filter LEUART output through pulse generator and the LEUART input through the pulse extender.
PULSEW
Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.
Reserved
REGFREEZE
When set, the update of the LEUART is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Reserved
PULSECTRL
Set when the value written to LEUARTn_PULSECTRL is being synchronized.
Name
Name
Name
Value
0
1
Value
0
1
Mode
UPDATE
FREEZE
Description
Filter is disabled. Pulses must be at least 2 cycles long for reliable detection.
Filter is enabled. Pulses must be at least 3 cycles long for reliable detection.
0
0
0x0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
R
Access
Access
Access
Description
Each write access to a LEUART register is updated into the Low Frequency domain
as soon as possible.
The LEUART is not updated with the new written value.
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241
Bit Position
Bit Position
Pulse Filter
Pulse Generator/Extender Enable
Pulse Width
Register Update Freeze
LEUARTn_PULSECTRL Register Busy
Description
Description
Description
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