EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 212

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.18 USARTn_IFS - Interrupt Flag Set Register
15.5.19 USARTn_IFC - Interrupt Flag Clear Register
31:13
12
11
10
9
8
7
6
5
4
3
2:1
0
Offset
0x044
Reset
Access
Name
Bit
Offset
0x048
Reset
Access
Name
2010-12-21 - d0034_Rev0.90
Reserved
CCF
Write to 1 to set the CCF interrupt flag.
SSM
Write to 1 to set the SSM interrupt flag.
MPAF
Write to 1 to set the MPAF interrupt flag.
FERR
Write to 1 to set the FERR interrupt flag.
PERR
Write to 1 to set the PERR interrupt flag.
TXUF
Write to 1 to set the TXUF interrupt flag.
TXOF
Write to 1 to set the TXOF interrupt flag.
RXUF
Write to 1 to set the RXUF interrupt flag.
RXOF
Write to 1 to set the RXOF interrupt flag.
RXFULL
Write to 1 to set the RXFULL interrupt flag.
Reserved
TXC
Write to 1 to set the TXC interrupt flag.
Name
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Access
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212
Bit Position
Bit Position
Set Collision Check Fail Interrupt Flag
Set Slave-Select in Master mode Interrupt Flag
Set Multi-Processor Address Frame Interrupt Flag
Set Framing Error Interrupt Flag
Set Parity Error Interrupt Flag
Set TX Underflow Interrupt Flag
Set TX Overflow Interrupt Flag
Set RX Underflow Interrupt Flag
Set RX Overflow Interrupt Flag
Set RX Buffer Full Interrupt Flag
Set TX Complete Interrupt Flag
Description
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