EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 168

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.5.12 I2Cn_IFS - Interrupt Flag Set Register
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
31:17
Bit
Offset
0x02C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Set on each clock low timeout. The timeout value can be set in CLTO bitfield in the I2Cn_CTRL register.
BITO
Set on each bus idle timeout. The timeout value can be set in the BITO bitfield in the I2Cn_CTRL register.
RXUF
Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.
TXOF
Set when data is written to the transmit buffer while the transmit buffer is full.
BUSHOLD
Set when the bus becomes held by the I
BUSERR
Set when a bus error is detected. The bus error is resolved automatically, but the current transfer is aborted.
ARBLOST
Set when arbitration is lost.
MSTOP
Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition,
then the MSTOP interrupt flag is not set.
NACK
Set when a NACK has been received.
ACK
Set when an ACK has been received.
RXDATAV
Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read.
TXBL
Set when the transmit buffer becomes empty. Cleared automatically when new data is written to the transmit buffer.
TXC
Set when the transmit shift register becomes empty and there is no more data in the transmit buffer.
ADDR
Set when incoming address is accepted, i.e. own address or general call address is received.
RSTART
Set when a repeated start condition is detected.
START
Set when a start condition is successfully transmitted.
Reserved
Name
Name
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
C module.
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Access
Access
...the world's most energy friendly microcontrollers
168
Bit Position
Bus Idle Timeout Interrupt Flag
Receive Buffer Underflow Interrupt Flag
Transmit Buffer Overflow Interrupt Flag
Bus Held Interrupt Flag
Bus Error Interrupt Flag
Arbitration Lost Interrupt Flag
Master STOP Condition Interrupt Flag
Not Acknowledge Received Interrupt Flag
Acknowledge Received Interrupt Flag
Receive Data Valid Interrupt Flag
Transmit Buffer Level Interrupt Flag
Transfer Completed Interrupt Flag
Address Interrupt Flag
Repeated START condition Interrupt Flag
START condition Interrupt Flag
Description
Description
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