EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 210

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register
29
28
27
26:25
24:16
15
14
13
12
11
10:9
8:0
31:16
15:8
7:0
Bit
Offset
0x03C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Set to disable transmitter and release data bus directly after transmission.
TXBREAK1
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of USARTn_WDATA.
TXTRIAT1
Set to tristate transmitter by setting TXTRI after transmission.
UBRXAT1
Set clear RXBLOCK after transmission, unblocking the receiver.
Reserved
TXDATA1
Second frame to write to FIFO.
RXENAT0
Set to enable reception after transmission.
TXDISAT0
Set to disable transmitter and release data bus directly after transmission.
TXBREAK0
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of WDATA.
TXTRIAT0
Set to tristate transmitter by setting TXTRI after transmission.
UBRXAT0
Set clear RXBLOCK after transmission, unblocking the receiver.
Reserved
TXDATA0
First frame to write to buffer.
Reserved
TXDATA1
Second frame to write to buffer.
TXDATA0
First frame to write to buffer.
Name
Name
0
0
0
0x000
0
0
0
0
0
0x000
0x00
0x00
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W
W
W
W
W
W
W
W
W
W
W
W
Access
Access
...the world's most energy friendly microcontrollers
210
Bit Position
Transmit Data As Break
Set TXTRI After Transmission
Unblock RX After Transmission
TX Data
Enable RX After Transmission
Clear TXEN After Transmission
Transmit Data As Break
Set TXTRI After Transmission
Unblock RX After Transmission
TX Data
TX Data
TX Data
Description
Description
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