EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 418

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.5.12 DACn_CAL - Calibration Register
25.5.13 DACn_BIASPROG - Bias Programming Register
27:16
15:12
11:0
31:23
22:16
15:14
13:8
7:6
5:0
31:15
14
Bit
Offset
0x02C
Reset
Access
Name
Bit
Offset
0x030
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
CH1DATA
Data written to this register will be written to DATA in DACn_CH1DATA.
Reserved
CH0DATA
Data written to this register will be written to DATA in DACn_CH0DATA.
Reserved
GAIN
This register contains the gain calibration value. This field is set to the production gain calibration value for the 1V25 internal reference
during reset, hence the reset value might differ from device to device. The field is unsigned. Higher values lead to lower DAC results.
Reserved
CH1OFFSET
This register contains the offset calibration value used with channel 1 conversions. This field is set to the production channel 1 offset
calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is
sign-magnitude encoded. Higher values lead to lower DAC results.
Reserved
CH0OFFSET
This register contains the offset calibration value used with channel 0 conversions. This field is set to the production channel 0 offset
calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is
sign-magnitude encoded. Higher values lead to lower DAC results.
Reserved
OPA2HALFBIAS
Name
Name
Name
0x000
0x000
0x40
0x00
0x00
1
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W
W
RW
RW
RW
RW
Access
Access
Access
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418
Bit Position
Bit Position
Channel 1 Data
Channel 0 Data
Gain Calibration Value
Channel 1 Offset Calibration Value
Channel 0 Offset Calibration Value
Half Bias Current
Description
Description
Description
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