EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 42

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter
7.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase
31:20
19:0
31:17
16
15:6
5:0
Offset
0x048
Reset
Access
Name
Bit
Offset
0x050
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
CACHEMISSES
Use to measure cache performance for a particular code section.
Reserved
PERIOD
Decides whether TIMEBASE specifies the number of AUX cycles in 1 us or 5 us
Reserved
BASE
Should be set to the number of AUX clock cycles-1 in 1us +10% if PERIOD is cleared, or the number of AUX clock cycles-1 in 5us
+10% if PERIOD is set. The value should be rounded up to make sure the number of clock cycles generate at least the specified
time. The resetvalue of the timebase matches a 14 MHz AUXHFRCO, which is the default frequency of the AUXHFRCO.
Name
Name
Value
0
1
Mode
1US
5US
0x00000
0
0x10
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
RW
RW
Access
Access
Description
TIMEBASE period is 1 us
TIMEBASE period is 5 us
...the world's most energy friendly microcontrollers
Bit Position
Bit Position
42
Cache misses since last performance counter start command.
Sets the timebase period
Timebase used by MSC to time flash writes and erases
Description
Description
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