EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 278

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.7 RTC_IFC - Interrupt Flag Clear Register
18.5.8 RTC_IEN - Interrupt Enable Register
31:3
2
1
0
31:3
2
1
0
31:3
2
1
0
Bit
Offset
0x018
Reset
Access
Name
Bit
Offset
0x01C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
COMP1
Write to 1 to set the COMP1 interrupt flag
COMP0
Write to 1 to set the COMP0 interrupt flag
OF
Write to 1 to set the OF interrupt flag
Reserved
COMP1
Write to 1 to clear the COMP1 interrupt flag
COMP0
Write to 1 to clear the COMP0 interrupt flag
OF
Write to 1 to clear the OF interrupt flag
Reserved
COMP1
Enable interrupt on compare match 1
COMP0
Enable interrupt on compare match 0
OF
Name
Name
Name
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
RW
RW
RW
Access
Access
Access
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278
Bit Position
Bit Position
Set Compare match 1 Interrupt Flag
Set Compare match 0 Interrupt Flag
Set Overflow Interrupt Flag
Clear Compare match 1 Interrupt Flag
Clear Compare match 0 Interrupt Flag
Clear Overflow Interrupt Flag
Compare Match 1 Interrupt Enable
Compare Match 0 Interrupt Enable
Overflow Interrupt Enable
Description
Description
Description
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