EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 192

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.3.5 Synchronous Half Duplex Communication
15.3.3.6 I2S
15.3.3.6.1 Word Format
15.3.3.6.2 Major Modes
2010-12-21 - d0034_Rev0.90
Half duplex communication in synchronous mode is very similar to half duplex communication in
asynchronous mode as detailed in Section 15.3.2.6 (p. 183) . The main difference is that in this mode,
the master must generate the bus clock even when it is not transmitting data, i.e. it must provide the
slave with a clock to receive data. To generate the bus clock, the master should transmit data with the
transmitter tristated, i.e. TXTRI in USARTn_STATUS set, when receiving data. If 2 bytes are expected
from the slave, then transmit 2 bytes with the transmitter tristated, and the slave uses the generated
bus clock to transmit data to the master. TXTRI can be set by setting the TXTRIEN command bit in
USARTn_CMD.
Note
I2S is a synchronous format for transmission of audio data. The frame format is 32-bit, but since data is
always transmitted with MSB first, an I2S device operating with 16-bit audio may choose to only process
the 16 msb of the frame, and only transmit data in the 16 msb of the frame.
In addition to the bit clock used for regular synchronous transfers, I2S mode uses a separate word clock.
When operating in mono mode, with only one channel of data, the word clock pulses once at the start of
each new word. In stereo mode, the word clock toggles at the start of new words, and also gives away
whether the transmitted word is for the left or right audio channel; A word transmitted while the word
clock is low is for the left channel, and a word transmitted while the word clock is high is for the right.
When operating in I2S mode, the CS pin is used as a the word clock. In master mode, this is automatically
driven by the USART, and in slave mode, the word clock is expected from an external master.
The general I2S word format is 32 bits wide, but the USART also supports 16-bit and 8-bit words. In
addition to this, it can be specified how many bits of the word should actually be used by the USART.
These parameters are given by FORMAT in USARTn_I2SCTRL.
As an example, configuring FORMAT to using a 32-bit word with 16-bit data will make each word on the
I2S bus 32-bits wide, but when receiving data through the USART, only the 16 most significant bits of
each word can be read out of the USART. Similarly, only the 16 most significant bits have to be written
to the USART when transmitting. The rest of the bits will be transmitted as zeroes.
The USART supports a set of different I2S formats as shown in Table 15.9 (p. 192) , but it is not limited
to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to
create an appropriate format. MONO enables mono mode, i.e. one data stream instead of two which is
the default. JUSTIFY aligns data within a word on the I2S bus, either left or right which can bee seen in
figures Figure 15.18 (p. 193) and Figure 15.19 (p. 194) . Finally, DELAY specifies whether a new I2S
word should be started directly on the edge of the word-select signal, or one bit-period after the edge.
Table 15.9. USART I2S Modes
Mode
Regular I2S
Left-Justified
Right-Justified
Mono
When operating as SPI slave in half duplex mode, TX has to be tristated (not disabled)
during data reception if the slave is to transmit data in the current transfer.
MONO
0
0
0
1
JUSTIFY
0
0
1
0
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192
DELAY
1
0
0
0
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CLKPOL
0
1
1
0