EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 202

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.3 USARTn_TRIGCTRL - USART Trigger Control register
11:10
9:8
7:4
3:0
31:7
6
5
4
3
2:0
Bit
Offset
0x008
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
PARITY
Determines whether parity bits are enabled, and whether even or odd parity should be used. Only available in asynchronous mode.
Reserved
DATABITS
This register sets the number of data bits in a USART frame.
Reserved
AUTOTXTEN
When set, AUTOTX is enabled as long as the PRS channel selected by TSEL has a high value
TXTEN
When set, the PRS channel selected by TSEL sets TXEN, enabling the transmitter on positive trigger edges.
RXTEN
When set, the PRS channel selected by TSEL sets RXEN, enabling the receiver on positive trigger edges.
Reserved
TSEL
Name
Name
Value
3
Value
0
2
3
Value
1
2
3
4
5
6
7
8
9
10
11
12
13
Mode
TWO
Mode
NONE
EVEN
ODD
Mode
FOUR
FIVE
SIX
SEVEN
EIGHT
NINE
TEN
ELEVEN
TWELVE
THIRTEEN
FOURTEEN
FIFTEEN
SIXTEEN
0x0
0x5
0
0
0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Description
The transmitter generates two stop bits. The receiver checks the first stop-bit only
Description
Parity bits are not used
Even parity are used. Parity bits are automatically generated and checked by hardware.
Odd parity is used. Parity bits are automatically generated and checked by hardware.
Description
Each frame contains 4 data bits
Each frame contains 5 data bits
Each frame contains 6 data bits
Each frame contains 7 data bits
Each frame contains 8 data bits
Each frame contains 9 data bits
Each frame contains 10 data bits
Each frame contains 11 data bits
Each frame contains 12 data bits
Each frame contains 13 data bits
Each frame contains 14 data bits
Each frame contains 15 data bits
Each frame contains 16 data bits
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202
Bit Position
Parity-Bit Mode
Data-Bit Mode
AUTOTX Trigger Enable
Transmit Trigger Enable
Receive Trigger Enable
Trigger PRS Channel Select
Description
Description
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