EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 204

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.5 USARTn_STATUS - USART Status Register
0
31:13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Offset
0x010
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
RXEN
Set to activate data reception on U(S)n_RX.
Reserved
RXFULLRIGHT
When set, the entire RX buffer contains right data. Only used in I2S mode
RXDATAVRIGHT
When set, reading RXDATA or RXDATAX gives right data. Else left data is read. Only used in I2S mode
TXBSRIGHT
When set, the TX buffer expects at least a single right data. Else it expects left data. Only used in I2S mode
TXBDRIGHT
When set, the TX buffer expects double right data. Else it may expect a single right data or left data. Only used in I2S mode
RXFULL
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one more
frame in the receive shift register.
RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
TXBL
Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if TXBIL is set,
TXBL is set whenever the transmit buffer is half-full or empty.
TXC
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when data is written to the
transmit buffer.
TXTRI
Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in USARTn_CTRL is set this bit
is always read as 0.
RXBLOCK
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
MASTER
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.
TXENS
Set when the transmitter is enabled.
RXENS
Name
Name
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
R
R
R
R
R
R
R
R
R
R
R
R
R
Access
Access
...the world's most energy friendly microcontrollers
204
Bit Position
Receiver Enable
RX Full of Right Data
RX Data Right
TX Buffer Expects Single Right Data
TX Buffer Expects Double Right Data
RX FIFO Full
RX Data Valid
TX Buffer Level
TX Complete
Transmitter Tristated
Block Incoming Data
SPI Master Mode
Transmitter Enable Status
Receiver Enable Status
Description
Description
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